The present invention relates to computer memory, and more specifically, to calibrating a reference voltage during runtime of the memory.
The introduction of double data rate fourth generation (DDR4) introduced Per DRAM Addressability (PDA) so that different dynamic random-access memory (DRAM) chips in the same DRAM module can have different parameters. That is, each chip in a group of DRAM chips (e.g., a rank) can have different parameters. Typically, PDA is used during the initial program load (IPL) when a DRAM module is booted—i.e., powered on. During IPL, the memory system can configure the parameters for each DRAM chip of the DRAM module. To do so, the DRAM module is placed in a PDA mode and the unique DRAM locations (e.g., registers) that define the parameters of each DRAM chip are programmed by using posted mode register set (MRS) commands, address inputs, and DQ data signals. Once programmed, the PDA mode is deactivated. The parameters are not typically adjusted after IPL is complete.